The present invention relates to a microprocessor and, more particularly, to an improvement in a microprocessor executing an instruction for accessing a memory.
In general, each instruction consists of an operation field and an operand code. The operation field has an operation code necessary to perform a required operation, whereas the operand field has information necessary to access a register, a memory, a peripheral unit and so forth.
In accordance with a demand for high performance of a microprocessor, a number of instructions, i.e. a number of operation codes must be prepared. For this purpose, it is considered to increase the number of bits allotted to the operation field. However, in an instruction for accessing a memory, it is required to increase the number of bits allotted to the operand field, since the operand field needs a register field portion having information indicative of a base register storing a base address and an offset data field portion having data indicative of an offset value from the base address.
As an instruction for accessing a memory, there are a LOAD instruction and a STORE instruction. The LOAD instruction is such that a data stored in a memory is transferred to a register incorporated in a microprocessor, and the STORE instruction is such that a data stored in a register is transferred to a memory. Moreover, the data transfer between the memory and register is required to be performed in byte units in addition to word units, half-word units and so on. Thus, it is required to prepare a plurality of LOAD instructions and STORE instructions in accordance with the number of bytes to be transferred, as disclosed in "MIPS R4000 Microprocessor User's Manual", 1991, pp. A-1 to A-9 and so on.
Specifically, of instructions as disclosed in the above Manual, there are, as shown in FIG. 1, a one-byte LOAD (STORE) instruction 410, a two-byte LOAD (STORE) instruction 420, a four-byte LOAD (STORE) instruction 430, and an eight-byte LOAD (STORE) instruction 410. Each of these instructions 410, 420, 430 and 440 consists of an operation field 11 composed of 6 bits (Bit Nos. 31-26) and an operand field 10 composed of 26 bits. The operand field 10 consists of a first field portion 12 composed of 5 bits (Bit Nos. 25-21) indicative of a first register, a second field portion 13 composed of 5 bits (Bit Nos. 20-16) indicative of a second register, and a third field portion 14 composed of 16 bits (Bit Nos. 15-0) indicative of an immediate data or an offset data. The second field portion 12 (rt) designates a source or destination register, and a memory address is obtained by adding the content of a register designated by the first field portion 12 (base) and the offset value of the third field portion 14.
The instructions 410, 420, 430 and 440 have individual operation codes (Op-code) as shown below, according to the number of bytes to be transferred:
______________________________________ Instruction Operation Code ______________________________________ One-Byte LOAD 100000 Two-Byte LOAD 100001 Four-Byte LOAD 100011 Eight-Byte LOAD 110111 One-Byte STORE 101000 Two-Byte STORE 101001 Four-Byte STORE 101011 Eight-Byte STORE 111111 ______________________________________
In a data transfer performed by the LOAD or STORE instruction, since the memory address is representative of a byte address, when the four-byte LOAD or STORE instruction is, for example, executed, the least significant two bits of the memory address must be set to "0" in order to transfer four-byte data simultaneously. To this end, the least significant two bits of the offset field portion 14 are required to written as "0". If at least one of these two bits is written with "1", there occurs trap exception to check a mis-alignment of the memory address.